CMOS (cornplementary MOS) is composed of pairs of complementary p-channel and n-channel MOSFETs. The reason why CMoS logic has become the most commonly used technology in integrated circuit design lies in its low power loss and better noise suppression capabilities. In fact, due to the demand for low power loss, only CMOS technology is currently used in ULSI manufacturing.
6.4.1 CMOS inverter
As shown in Figure 6.28, CMOS inverter is the basic unit of CMOS logic circuit. In a CMOS inverter, the gates of the p and n-channel transistors are connected together and serve as the input terminal of the inverter, and the drains of the two transistors are also connected together and serve as the output terminal of the inverter The source and substrate contacts of the n-channel MOSFET are both grounded, while the source and substrate of the p-channel MOSFET are connected to the power supply terminal (VDD). Note that both p-channel and n-channel MOSFETs are Enhancement transistor, when the input voltage is low voltage (that is, vin=O, VGsn=o|VTp| (VGSp and VTp are negative values), so the p-channel MOSFET is in the on state,
Therefore, the output terminal is charged to VDD through the p-channel MOSFET. When the input voltage gradually rises to make the gate voltage equal to VDD, since VGSn=VDD>VTn, the n-channel MOSFET will be turned on, and due to |VGSp| ≈O<|VTp|, so the p-channel MOSFET will be turned off. Therefore, the output terminal will be discharged to zero potential through the n-channel MOSFET,
To further understand the work of CMOS inverters, first draw the output characteristics of the transistor, as shown in Figure 6.29, where Ip and In are functions of the output voltage (Vout). Ip is the current flowing from the source (connected to VDD) to the drain (output terminal) of the p-channel MOSFET; In is the current flowing from the drain (output terminal) to the source (connected to the ground terminal) of the n-channel MOSFET
The current. It should be noted that under a fixed Vout, increasing the input voltage (vin) will increase In and decrease Ip, but in steady state, In should be the same as Ip. For a given Vin, it can be In(Vin) and Ip(Vin) The intercept of, and the corresponding Vout calculated as shown in Figure 6.29. The Vin-Vout curve shown in Figure 6.30 is called the transmission curve of the CMOS inverter.
An important characteristic of CMOS inverters is that when the output is in a logic steady state (ie Vout= or VDD), only one transistor is turned on, so the current flowing from the power supply to the ground is very small, and it is equivalent to a device Leakage current when closed. In fact, only a very short time when the two devices are temporarily turned on will a large current flow. Therefore, compared with other types of logic circuits such as n-channel MOSFETs and bipolar logic circuits, its steady state When the power loss is very low.